How to Calculate PCB Trace Width: IPC-2221 Formula, Copper Weight, and Layer-Type Corrections

Undersized PCB traces overheat and fail — sometimes immediately, sometimes gradually through insulation degradation that shortens product life. When a trace carries more current than its cross-section can dissipate as heat, the temperature rise accelerates resistance, which increases heating further, until solder joints reflow, laminates delaminate, or the copper fuses open like a slow fuse. This failure mode is entirely preventable: the IPC-2221 empirical formula predicts the minimum trace width required to keep temperature rise within a specified budget, and it has been the industry standard for PCB current-capacity sizing for decades.

The canonical IPC-2221 formula is I = k · ΔT^0.44 · A^0.725, where k = 0.048 for external layers and k = 0.024 for internal layers, ΔT is the allowable temperature rise in °C, and A is the required cross-sectional area in mils². This is not a derived physics equation — it is a curve fit to experimental data from MIL-STD-275 tests conducted in the 1950s. The formula is deliberately conservative: those original test boards were single traces with no adjacent copper, no ground planes, and no thermal paths other than the FR-4 substrate. Modern multilayer boards with copper pours and adjacent planes often handle significantly more current than IPC-2221 predicts.

Engineers use this formula at two points in the design cycle: first in schematic review to budget trace widths before layout begins, and second during layout review to verify that routed traces meet the budget. Missing this calculation in either phase creates the common failure mode where high-current traces are routed at the same width as signal traces — typically 6 to 8 mils — and then overheat in the field. The trace width calculator on this page implements the full IPC-2221 calculation in three modes: width-from-current, current-from-width, and verify-existing.

This guide covers the calculation method step by step, provides a lookup table of common current-to-width mappings, and works through four representative design examples from a 2 A power rail through USB-C VBUS at 5 A. It also covers the key distinction between external and internal layer traces, copper weight selection, and the most common sizing mistakes that cause field failures.

Why IPC-2221 Sets the Trace-Width Standard

PCB trace current capacity follows from thermal equilibrium: the rate of heat generation (I²R) must balance the rate of heat dissipation through the substrate and air. The IPC-2221 formula captures this balance empirically. Two constants, 0.44 and 0.725, are exponents fitted to the original test data. The 0.44 exponent on temperature rise reflects the nonlinear dependence of heat dissipation on temperature differential; the 0.725 exponent on area reflects two-dimensional heat spreading at the copper-substrate interface.

The standard defines separate k constants for external and internal layers because the thermal paths differ. External traces cool through both the FR-4 substrate and direct air convection. Internal traces are surrounded by FR-4 on all sides and rely entirely on conduction through the laminate. In the original test boards, this difference was captured by halving k: k = 0.048 for external, k = 0.024 for internal. In modern boards, the internal layer penalty is often overstated — an internal trace adjacent to a solid ground plane actually runs cooler than an isolated external trace, because copper conducts heat ten times better than FR-4. IPC-2152 (2009) addresses this with plane-proximity correction factors that IPC-2221 does not include.

For design work, IPC-2221 remains the standard first-order screening tool. It is required by many customers as a design verification step and is referenced explicitly in IPC-2221C (the current 2023 edition). Use IPC-2221 for initial sizing and for conservative verification; use IPC-2152 for high-current designs above 10 A or when detailed plane-proximity analysis is needed.

PCB Trace Width Chart by Current

For a quick lookup, here are typical minimum trace widths at 10 °C temperature rise for external 1 oz copper, calculated from the canonical IPC-2221 formula (k = 0.048):

Current	Width (mils)	Width (mm)	W rec 20% (mils)	Notes
0.5 A	4.5	0.11	5.4	Below fab minimum; use 6+ mils
1 A	11.8	0.30	14.2	Signal/control level
2 A	30.8	0.78	36.9	Common power rail
3 A	53.8	1.37	64.5	USB-C VBUS standard
5 A	108.8	2.76	130.5	USB-C VBUS extended
8 A	205.7	5.23	246.8	Motor driver typical
10 A	283.4	7.20	340.1	High-current power
15 A	491.7	12.49	590.0	Edge of IPC range
20 A	719.2	18.27	863.0	Bus bar territory
30 A	1231.2	31.27	1477.4	Beyond IPC-2221

For 2 oz copper, divide the trace width values by 2 (2 oz = 2.756 mils thick instead of 1.378 mils — practical widths roughly halve for the same current). For internal layers, multiply the cross-sectional area requirement by 2.6 (because k = 0.024 internal, half of external, propagated through the A^0.725 exponent).

These are IPC-2221 minimums based on the canonical formula. Add 20–50% manufacturing margin for production (the W rec column applies 20%). Check that your computed width is above your fab's minimum (typically 4–6 mils for standard processes) and that vias along the trace can handle the same current.

How to Calculate PCB Trace Width

The IPC-2221 calculation has four steps, all reproducible by hand or with a calculator:

Step 1: Choose IPC constant k based on layer type.
- External (outer) layer: k = 0.048
- Internal (buried) layer: k = 0.024

External layers cool through air convection. Internal layers conduct heat only through FR-4 substrate. Internal traces require roughly 2.6 times the cross-sectional area for the same current at the same temperature rise.

Step 2: Compute required cross-sectional area.

A = (I / (k · ΔT^0.44))^(1/0.725)

where I is current in amperes, ΔT is allowable temperature rise in degrees Celsius, and A is area in mils squared.

For I = 2 A, ΔT = 10 °C, k = 0.048 (external):
- 10^0.44 = 2.754
- 0.048 × 2.754 = 0.1322
- 2 / 0.1322 = 15.13
- A = 15.13^(1/0.725) = 15.13^1.3793 ≈ 42.4 mils²

Step 3: Look up copper thickness from copper weight.
- 0.5 oz/ft² → 0.689 mils → 17.5 μm
- 1 oz/ft² → 1.378 mils → 35 μm
- 2 oz/ft² → 2.756 mils → 70 μm
- 3 oz/ft² → 4.134 mils → 105 μm
- 4 oz/ft² → 5.512 mils → 140 μm

Step 4: Compute trace width.

W (mils) = A (mils²) / t (mils)
W (mm) = W (mils) · 0.0254

For 1 oz copper (t = 1.378 mils) at 2 A, 10 °C:
- W = 42.4 / 1.378 = 30.8 mils = 0.78 mm

Apply manufacturing margin (typically 20–50% above IPC minimum) and round up to your fab's grid (typically 1 mil or 0.05 mm). Check the result against your fab's minimum trace width.

IPC-2221 vs IPC-2152: Which Standard to Use

IPC-2221 has been the dominant trace-width standard for decades, but it carries a quiet limitation: the formula is curve-fitted to data from MIL-STD-275 tests conducted in the 1950s. The original test boards were single traces on unpopulated boards with no adjacent copper. Modern multilayer boards with ground planes, copper pours, and power planes cool traces far better than the IPC-2221 test setup, and real current capacity is often 2–3 times higher than IPC-2221 predicts.

IPC-2152 (2009) replaced the underlying data with new empirical tests on hundreds of board configurations. It accounts for plane proximity, board thickness, copper density, and substrate material. The result is a much larger standard — over 100 charts and figures versus IPC-2221's two charts — but with substantially better accuracy for modern board designs.

Use IPC-2221 for standard screening at moderate currents (under 10 A), single-layer or simple multilayer boards, hobbyist projects, educational use, or when a legacy specification explicitly requires it. The conservative result gives margin for unaccounted factors. Use IPC-2152 for high-current designs (10 A and above), production-critical reliability, modern multilayer boards where plane proximity matters, and any case where overdesigned traces would waste board area or limit routing.

External vs Internal Layer Traces

The IPC-2221 formula uses two different k constants for the two layer types: k = 0.048 for external layers and k = 0.024 for internal layers. The 2× difference reflects the original IPC-D-275 assumption that internal traces dissipate heat only through the FR-4 substrate, while external traces cool through both substrate and air convection.

The effect on required cross-section is larger than the 2× k ratio suggests. Because area appears with the 0.725 exponent in the formula, the required cross-sectional area for an internal trace at the same current and ΔT is 2^(1/0.725) ≈ 2.6× the external requirement. This means an internal trace on 1 oz copper needs 2.6 times the width of an external trace for the same current — not simply double.

In modern multilayer boards, the assumption is often incorrect. Internal traces adjacent to copper planes dissipate heat through the plane, which conducts heat 10 times better than FR-4. An internal trace next to a solid ground plane may run cooler than an isolated external trace with no adjacent copper. IPC-2152 captures this with plane-proximity correction factors. Routing high-current paths on external layers remains the default best practice because the worst-case IPC-2221 result is the most conservative, thermal verification through IR imaging is simpler, and repair and rework are easier.

Copper Weight and Trace Width

Copper weight, measured in ounces per square foot, sets the trace thickness. Doubling copper weight roughly halves the required trace width for the same current, because cross-sectional area is the product of width and thickness. A 1 oz 30 mil trace carries the same current as a 2 oz 15 mil trace at the same temperature rise.

Common copper weights and their practical implications:

• 0.5 oz (17.5 μm): Low-cost prototyping and signal-layer designs. Rarely used for power paths. Very narrow traces have high resistance; use sparingly for anything above milliamp signals.
• 1 oz (35 μm): The standard for most PCBs. Suitable for power rails up to 2–3 A on external layers with proper sizing. Most fab cost tiers include 1 oz outer copper as the default.
• 2 oz (70 μm): Power electronics, USB-C VBUS, motor driver outputs. Halves required width relative to 1 oz. Adds roughly 10–20% to bare board cost. The right choice for any design above 3 A that must fit in a compact routing envelope.
• 3 oz (105 μm): High-current power conversion, battery pack BMS. Reduces width further but requires specialized fab processes and adds significant cost. Still within IPC-2221 validity range.
• 4 oz (140 μm): Outside the IPC-2221 validity range; requires extrapolation. Used for extreme current designs and custom power modules.

Key Facts

PCB trace width follows from the IPC-2221 thermal model: I = k · ΔT^0.44 · A^0.725, where k = 0.048 (external) or 0.024 (internal), ΔT in °C, A in mils².

At 1 A on 1 oz external copper with 10 °C rise, minimum trace width is approximately 11.8 mils (0.30 mm). At 3 A this rises to 53.8 mils (1.37 mm). At 5 A, 108.8 mils (2.76 mm).

Doubling copper weight roughly halves required trace width for the same current, because cross-sectional area is the product of width and thickness.

Internal layer traces require approximately 2.6× the cross-section of external traces for the same current, per the canonical IPC-2221 formula (k_external / k_internal = 2, but because of the 0.725 exponent on area in the formula, the cross-section ratio is 2^(1/0.725) ≈ 2.6×). Modern boards with adjacent planes often perform better than this estimate.

IPC-2221 is conservative for modern multilayer boards. IPC-2152 (2009) provides empirically-tested data with plane-proximity corrections and typically permits narrower traces.

Practical fab minimums are 4–6 mils (0.10–0.15 mm) for standard processes. Even if the calculator returns a narrower trace, the board cannot be manufactured below this limit.

Vias are often the bottleneck in high-current paths. A standard 0.3 mm drill via with 1 oz copper carries roughly 0.5–1 A continuously as a rough screening estimate. Higher currents require multiple parallel vias or larger drills.

Temperature rise (ΔT) and absolute temperature (T_ambient) follow different unit conversions. ΔT in °F converts as × 5/9 (no offset); T_ambient in °F converts as (T − 32) · 5/9 (offset).

Final trace temperature = T_ambient + ΔT. For automotive under-hood applications with 125 °C ambient and 10 °C rise, final trace temperature is 135 °C — close to the lower end of FR-4 glass transition (Tg 130–180 °C).

Apply 20–50% manufacturing margin on top of the IPC-2221 minimum. Critical applications and harsh environments warrant the higher end of this range.

The narrowest continuous segment of a current path controls local heating. Check connector escape regions, IC pad neck-downs, fuse mountings, and via escapes separately from the bulk trace.

Example Calculation 1 — Power Supply Output (2 A, External 1 oz)

Inputs: Current = 2 A, ΔT = 10 °C, Copper weight = 1 oz (default), Layer type = external (default), Trace length = 50 mm, Application = power-electronics, Design margin = 20% (default)

Step 1: IPC constant for external layer.
k = 0.048

Step 2: Cross-sectional area.
- A = (2 / (0.048 · 10^0.44))^(1/0.725)
- = (2 / (0.048 · 2.754))^(1/0.725)
- = (2 / 0.1322)^1.3793
- = (15.13)^1.3793
- ≈ 42.4 mils² ≈ 0.0274 mm²

Step 3: Copper thickness.
1 oz → 1.378 mils → 35 μm

Step 4: Trace width.
W = 42.4 / 1.378 ≈ 30.8 mils ≈ 0.78 mm

Step 5: Recommended width with 20% margin.
W_rec = 30.8 · 1.20 ≈ 36.9 mils ≈ 0.94 mm

Step 6: Resistance, voltage drop, power.
- Mean trace temp T_mean = 25 + 10/2 = 30 °C
- ρ_copper(30 °C) ≈ 1.72 × 10⁻⁸ · (1 + 0.00393 · 10) ≈ 1.79 × 10⁻⁸ Ω·m
- A_SI = 42.4 · 6.4516 × 10⁻¹⁰ ≈ 2.735 × 10⁻⁸ m²; L_SI = 0.050 m
- R = 1.79 × 10⁻⁸ · 0.050 / 2.735 × 10⁻⁸ ≈ 32.7 mΩ
- V_drop = 2 · 0.0327 ≈ 65.4 mV
- P = 4 · 0.0327 ≈ 130.8 mW

Result: PCB Status: NORMAL / MODERATE-CURRENT. Minimum trace width: 30.8 mils (0.78 mm). Recommended width: 36.9 mils (0.94 mm) with 20% margin. Cross-section: 42.4 mils² (0.0274 mm²). Copper thickness: 1.378 mils (35 μm). Trace resistance: 32.7 mΩ at 50 mm length. DC voltage drop: 65.4 mV at 2 A. Power dissipation: 130.8 mW.

Engineering interpretation: a 1 oz external trace 36 mils wide and 50 mm long handles 2 A with 10 °C rise and minimal voltage drop. This is well within typical fab capability (36 mils is generous) and leaves headroom for transients.

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Example Calculation 2 — Current-from-Width (Internal 20 mil, 2 oz)

Inputs: Trace width = 20 mil, ΔT = 20 °C, Copper weight = 2 oz, Layer = internal, Current = blank (current-from-width mode)

Step 1: k = 0.024 (internal), t = 2.756 mils (2 oz)

Step 2: Actual cross-section.
A_actual = 20 × 2.756 = 55.12 mils²

Step 3: Maximum current.
- I_max = 0.024 · 20^0.44 · 55.12^0.725
- 20^0.44 ≈ 3.472; 55.12^0.725 ≈ 19.71
- I_max ≈ 0.024 · 3.472 · 19.71 ≈ 1.64 A

Result: PCB Status: NORMAL / MODERATE-CURRENT. Maximum current: 1.64 A. The same trace on an external layer (k = 0.048) would carry approximately 2.4 A at the same ΔT — 2 oz external with 20 mil width handles considerably more than the internal-layer version.

Engineering interpretation: a 20 mil 2 oz internal trace with 20 °C rise budget carries 1.64 A. If the design needs 2 A continuous, either move the trace to an external layer, widen it, or add copper weight.

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Example Calculation 3 — Verify-Existing Severely Undersized (External 10 mil for 3 A)

Inputs: Current = 3 A, Trace width = 10 mil (designed, marginal), ΔT = 10 °C, Copper weight = 1 oz, Layer type = external, Application = power-electronics, Design margin = 20%

Step 1: Required cross-sectional area.
- A_required = (3 / (0.048 · 10^0.44))^(1/0.725)
- = (3 / 0.1322)^1.3793
- = (22.69)^1.3793
- ≈ 74.2 mils²

Step 2: Required trace width.
W_required = 74.2 / 1.378 ≈ 53.8 mils ≈ 1.37 mm

Step 3: Recommended width with 20% margin.
W_recommended = 53.8 · 1.20 ≈ 64.6 mils ≈ 1.64 mm

Step 4: Deviation of designed width.
Δ_min = (10 − 53.8) / 53.8 · 100% ≈ −81.4%

The trace is 81.4% below the IPC-2221 minimum. Report the absolute value: "designed trace width 10 mil is 81.4% below the IPC-2221 minimum."

Step 5: Status classification.
|Δ_min| > 10% → SEVERELY-UNDERSIZED

Step 6: Maximum current the designed 10 mil trace can carry.
- A_actual = 10 · 1.378 = 13.78 mils²
- I_max_actual = 0.048 · 10^0.44 · 13.78^0.725 ≈ 0.048 · 2.754 · 6.70 ≈ 886 mA

Result: PCB Status: SEVERELY-UNDERSIZED. Designed trace width: 10 mil (0.25 mm). IPC-2221 minimum: 53.8 mil (1.37 mm), deviation 81.4% below. Recommended with margin: 64.6 mil (1.64 mm). Maximum current at 10 mil: 886 mA.

Engineering interpretation: the 10 mil designed trace can carry only 886 mA at 10 °C rise per IPC-2221 — far below the 3 A target. To handle 3 A: widen to 53.8 mil (or 64.6 mil with margin), move to 2 oz copper which roughly halves required width, or parallel multiple traces across layers.

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Example Calculation 4 — USB-C VBUS at 5 A (1 oz vs 2 oz)

Inputs: Current = 5 A, ΔT = 10 °C, Layer type = external, Application = usb-power-delivery, Compare 1 oz and 2 oz copper.

1 oz copper case:
- A = (5 / (0.048 · 10^0.44))^(1/0.725) = (5 / 0.1322)^1.3793 = (37.82)^1.3793 ≈ 149.9 mils²
- t = 1.378 mils
- W = 149.9 / 1.378 ≈ 108.8 mils ≈ 2.76 mm
- W_rec (20% margin) ≈ 130.5 mils ≈ 3.32 mm

2 oz copper case:
Same area required (149.9 mils²) but thicker copper.
- t = 2.756 mils
- W = 149.9 / 2.756 ≈ 54.4 mils ≈ 1.38 mm
- W_rec (20% margin) ≈ 65.3 mils ≈ 1.66 mm

Result comparison:
- 1 oz external: 109 mil minimum, 131 mil recommended
- 2 oz external: 54 mil minimum, 65 mil recommended

Engineering interpretation: USB-C VBUS at 5 A on 1 oz copper demands a 2.8–3.3 mm wide trace, which strains routing budget on a compact board. Moving to 2 oz copper halves the required width to 1.4–1.7 mm — fits much more comfortably in typical USB-C designs. The 10–20% upcharge for 2 oz copper usually pays back in routing flexibility and reduced via count.

Soft checks at 5 A: USB-PD-COMPLIANCE-NOTICE fires. VIA-BOTTLENECK-NOTICE fires. Verify connector escape region neck-down separately. Stitch any layer transitions with multiple vias. Verify end-to-end DC resistance from connector through protection devices to load.

PCB Trace Width for USB-C Power Delivery

USB Power Delivery (USB-PD) introduces VBUS currents that push past the comfortable range of standard PCB design. Profile currents are:
- USB-PD Standard: 3 A at 5/9/15/20 V
- USB-PD Extended: 5 A at 9/15/20 V (requires e-marker cable)
- USB-PD EPR: up to 5 A at higher voltages (Extended Power Range)

At 5 A on 1 oz external copper with 10 °C rise, the IPC-2221 minimum trace width is about 109 mils (2.76 mm). For production designs, plan 130–160 mils (3.3–4 mm) with 20–50% manufacturing margin, or move to 2 oz copper which roughly halves the required width to 54–65 mils (1.4–1.65 mm).

The connector escape region is the hardest part. USB-C receptacle pin pitch forces neck-down between the connector and the bulk VBUS trace. Make this neck-down as short as possible, use the full available pad area, and consider stitching with multiple vias if changing layers.

Vias on the VBUS path are often the bottleneck. A standard 0.3 mm drill via with 1 oz plating carries roughly 0.5–1 A continuously as a rough screening estimate. For 5 A through a via stack, use 4–8 parallel vias with adequate plating thickness, or specify larger drill diameter (0.4–0.5 mm).

Where PCB Trace Sizing Goes Wrong

Using Peak Current Instead of RMS

Inrush current, startup surges, and motor lock-rotor currents can be 5–10× the continuous operating current. These transients last milliseconds, not seconds, and do not heat the trace the same way continuous current does. Sizing a trace for 10 A inrush when the continuous current is 2 A means a trace that is five times wider than necessary. Use RMS or continuous current for IPC-2221 thermal sizing; verify peak currents separately against copper fusing and protection device ratings.

Ignoring Fab Process Minimums

Standard PCB processes have minimum trace widths of 4–6 mils (0.10–0.15 mm). Even if the calculator returns a 3 mil trace, the board cannot be manufactured below the fab's minimum. At sub-amp signal currents, the IPC-2221 result often falls below fab minimums — the right answer is to use the fab minimum as the floor, not to narrow the trace to the calculated value.

Forgetting Vias in the Current Path

A trace sized for 5 A carries 5 A along its length, but a single standard via on that path may limit the path to 0.5–1 A. High-current paths must be checked at every layer change: each via needs sufficient plating thickness, drill diameter, and annular ring area. Multiple parallel vias — four to eight for currents above 3 A — are the standard solution. Specifying filled vias with sufficient copper fill further improves capacity.

Treating Temperature Rise as an Absolute Temperature

ΔT is the rise above ambient — it is a temperature difference, not an absolute temperature. When entered in Fahrenheit, it converts as × 5/9 with no offset. Ambient temperature converts with the offset formula: (T_F − 32) · 5/9. Treating ΔT = 18 °F as an absolute temperature, applying the offset conversion, produces a completely wrong result. The calculator handles this automatically; manual calculations must apply the right formula to each variable.

Sizing Bulk Traces but Ignoring Neck-Downs

The narrowest continuous segment controls local heating. A power rail may be 60 mils wide across most of its run, but if it passes through a connector escape between 16 mil pads, that 16 mil neck-down is the thermal bottleneck. Design rules and DRC tools catch electrical clearances but do not check current-carrying capacity at neck-down points. Verify every narrow segment explicitly: connector escapes, IC pad breakouts, fuse mounts, and via escapes.

IPC-2221 Validity Range and Out-of-Range Warnings

The original IPC-2221 test boards covered a specific range of parameters. Results are reliable within this range; the calculator extrapolates beyond it and displays an advisory:
- Current: 0 to 35 A
- ΔT: 10 to 100 °C
- Copper weight: 0.5 to 3 oz/ft²
- Trace width: up to 400 mils (10.16 mm)

Common cases that trigger extrapolation warnings: high-current battery pack traces above 35 A, 4 oz copper boards, computed widths above 400 mils (bus bar or copper-pour territory), and temperature rises above 100 °C for extreme thermal designs. For designs in this region, route through IPC-2152 charts or full thermal simulation.

FAQ

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