PCB Trace Width Calculator

Calculate

Design current the trace must carry. Use continuous or RMS current for thermal sizing.

Maximum allowable temperature rise above ambient. 10 °C conservative; 20 °C for power circuits. Temperature difference, not absolute temperature.

Mode, trace width/length, copper weight, layer, ambient temperature, application context, design margin (all optional — defaults: 1 oz external, auto mode, 20% margin, 77 °F ambient).

Overview

This calculator sizes copper traces on printed circuit boards using the IPC-2221 industry standard. Enter the design current and allowable temperature rise; the tool returns the minimum trace width required to keep the trace below the temperature budget, the recommended width with manufacturing margin, the cross-sectional area, and (when trace length is provided) resistance, DC voltage drop, and power dissipation.

Three calculation modes cover the common decisions a hardware engineer or PCB designer faces. Width-from-current is the default: enter current, get minimum trace width. Current-from-width is the reverse: enter an existing or planned trace width, get the maximum current it can safely carry. Verify-existing compares a designed trace against the IPC-2221 minimum and the selected design margin, flagging undersized traces before they ship.

The calculator implements the empirical IPC-2221 formula I = k · ΔT^0.44 · A^0.725, where k = 0.048 for external layers and k = 0.024 for internal layers. It supports copper weights 0.5 oz through 4 oz, temperature rises from a fraction of a degree up through the IPC-2221 validity range (10 to 100 °C), and currents from milliamps through 35 A (and beyond, with extrapolation warnings).

Both Imperial (mils, inches) and Metric (mm, μm) units are supported throughout. Mils and millimeters interconvert at 1 mil = 0.0254 mm. PCB fab manufacturing minimums commonly land at 4–6 mils (0.1–0.15 mm) for standard processes, with premium fabs offering 3 mils or finer.

Typical users include hardware engineers sizing power rails on a new board, USB-C designers checking VBUS trace widths for 3 A and 5 A power delivery, motor driver layout designers verifying H-bridge outputs, automotive electronics teams working in higher ambient temperatures, hobbyist makers double-checking before sending a board to fabrication, and students learning the IPC-2221 thermal model.

The result is a first-order screening tool grounded in the IPC-2221 empirical formula. It does not run hourly thermal simulation, does not model copper pour interaction beyond a general advisory, does not compute RF characteristic impedance, and does not predict transient fault current behavior. For high-current designs above 10 A or critical applications, use IPC-2152 charts (the modern empirical replacement from 2009) or full thermal simulation.

How to Use the PCB Trace Width Calculator

  1. Enter the design current the trace must carry. Use continuous or RMS current for thermal sizing; short fault or startup pulses require separate transient analysis. Choose amperes or milliamperes based on magnitude.

  2. Enter the allowable temperature rise (ΔT) above ambient. 10 °C is a common conservative design rise. 20 °C is often used for power circuits. ΔT is a temperature difference, not an absolute temperature.

  3. Open advanced parameters if you want to change defaults. Copper weight defaults to 1 oz. Layer type defaults to external. Calculation mode defaults to auto, which infers the mode from which fields are filled.

  4. Optional inputs refine the result: trace width (for reverse or verify modes), trace length (enables resistance and voltage drop output), ambient temperature, application context (for guidance, not math), and design margin (20% default, 50% for harsh environments, or custom).

  5. Press Calculate. The Results panel shows minimum trace width with imperial and metric units, recommended width with margin, cross-sectional area, copper thickness, layer type, and current regime.

  6. Review the Result Explanation for status-specific guidance and any soft-check warnings (IPC-2221 range, fab minimum, via bottleneck, temperature limits, USB-PD compliance, automotive context).

In auto mode: fill only Current → width-from-current mode; fill only Trace Width → current-from-width mode; fill both → verify-existing mode.

Formula

IPC-2221 Current-Carrying Capacity:

I = k · ΔT^0.44 · A^0.725

where:

  • I = current in amperes
  • ΔT = allowable temperature rise in °C above ambient
  • A = cross-sectional area in mils²
  • k = 0.048 (external layers) or 0.024 (internal layers)

Solved for cross-sectional area (width-from-current):

A = (I / (k · ΔT^0.44))^(1/0.725)

Trace width from area:

W (mils) = A (mils²) / t (mils)

Where t is copper thickness: 0.5 oz → 0.689 mil, 1 oz → 1.378 mil, 2 oz → 2.756 mil, 3 oz → 4.134 mil, 4 oz → 5.512 mil

Resistance, voltage drop, power (optional, when trace length provided):

ρ_copper(T) = 1.72×10⁻⁸ · (1 + 0.00393 · (T_mean − 20)) Ω·m

T_mean = T_ambient + ΔT/2

R = ρ · L / A_SI

V_drop = I · R

P_diss = I² · R

PCB Trace Width Chart by Current

For a quick lookup, here are typical minimum trace widths at 10 °C temperature rise for external 1 oz copper, calculated from the IPC-2221 formula:

Current Width (mils) Width (mm) Notes
0.5 A 5 0.13 Below fab minimum; use 6+ mils
1 A 12 0.30 Signal/control level
2 A 28 0.72 Common power rail
3 A 49 1.24 USB-C VBUS standard
5 A 100 2.54 USB-C VBUS extended
8 A 189 4.80 Motor driver typical
10 A 260 6.60 High-current power
15 A 451 11.46 Edge of IPC range
20 A 660 16.76 Bus bar territory
30 A 1130 28.70 Beyond IPC-2221

For 2 oz copper, multiply the cross-sectional area requirement by the same value, but divide by 2 oz (2.756 mils thick) instead of 1 oz (1.378 mils thick) — practical widths roughly halve. For internal layers, widths roughly double because k = 0.024 instead of 0.048.

These are IPC-2221 minimums. Add 20–50% manufacturing margin for production. Check that your computed width is above your fab's minimum (typically 4–6 mils for standard processes) and that vias along the trace can handle the same current.

How to Calculate PCB Trace Width

The IPC-2221 calculation has four steps, all reproducible by hand or with a calculator:

Step 1: Choose IPC constant k based on layer type.

  • External (outer) layer: k = 0.048
  • Internal (buried) layer: k = 0.024

External layers cool through air convection. Internal layers conduct heat only through FR-4 substrate. Internal traces require roughly twice the cross-sectional area for the same current at the same temperature rise.

Step 2: Compute required cross-sectional area.

A = (I / (k · ΔT^0.44))^(1/0.725)

where I is current in amperes, ΔT is allowable temperature rise in degrees Celsius, and A is area in mils squared.

Step 3: Look up copper thickness from copper weight.

  • 0.5 oz/ft² → 0.689 mils → 17.5 μm
  • 1 oz/ft² → 1.378 mils → 35 μm
  • 2 oz/ft² → 2.756 mils → 70 μm
  • 3 oz/ft² → 4.134 mils → 105 μm
  • 4 oz/ft² → 5.512 mils → 140 μm

Step 4: Compute trace width.

  • W (mils) = A (mils²) / t (mils)
  • W (mm) = W (mils) × 0.0254

Apply manufacturing margin (typically 20–50% above IPC minimum) and round up to your fab's grid.

IPC-2221 vs IPC-2152: Which Standard to Use

IPC-2221 has been the dominant trace-width standard for decades, but it carries a quiet limitation: the formula is curve-fit to data from MIL-STD-275 tests conducted in the 1950s. The original test boards were single traces on unpopulated boards with no adjacent copper. Modern multilayer boards with ground planes, copper pours, and power planes cool traces far better than the IPC-2221 test setup did, and real current capacity is often 2–3 times higher than IPC-2221 predicts.

IPC-2152 (2009) replaced the underlying data with new empirical tests on hundreds of board configurations. It accounts for plane proximity, board thickness, copper density, and substrate material. The result is a much larger standard (over 100 charts and figures vs IPC-2221's two charts) but with substantially better accuracy.

When to use IPC-2221: standard screening for moderate currents (under 10 A), single-layer or simple multilayer boards, hobbyist projects, educational use, or when a legacy specification explicitly requires it. The conservative result gives margin for unaccounted factors.

When to use IPC-2152: high-current designs (10 A and above), production-critical reliability, modern multilayer boards where plane proximity matters, and any case where overdesigned traces would waste board area or limit routing.

IPC-2221 Validity Range

The original IPC-2221 test boards covered a specific range of parameters. The calculator returns reliable results within this range and extrapolates beyond it with an advisory warning.

Validity bounds (from the original IPC-D-275 and MIL-STD-275 data):

  • Current: 0 to 35 A
  • ΔT: 10 to 100 °C
  • Copper weight: 0.5 to 3 oz/ft²
  • Trace width: up to 400 mils (10.16 mm)

When any of these four bounds is exceeded, the calculator classifies the result as OUT-OF-IPC-RANGE and displays an advisory message. Common cases that trigger extrapolation:

  • High-current power electronics above 35 A (battery pack bus, motor controller outputs, switching regulators)
  • 4 oz copper boards (require specialized fabrication; not all fabs support this weight)
  • Computed trace widths above 400 mils (bus bar or copper-pour territory)
  • Temperature rise above 100 °C (extreme thermal designs)

For designs in this region, route through IPC-2152 charts (modern 2009 standard with broader empirical coverage) or through full thermal simulation.

External vs Internal Layer Traces

The IPC-2221 formula uses two different constants for the two layer types:

  • External layers: k = 0.048
  • Internal layers: k = 0.024

The 2× difference reflects the original IPC-D-275 assumption that internal traces dissipate heat only through the FR-4 substrate, while external traces cool through both substrate and air convection. In the original test boards this was roughly true.

In modern multilayer boards, the assumption is often incorrect. Internal traces adjacent to copper planes dissipate heat through the plane, which conducts heat 10 times better than FR-4. An internal trace next to a solid ground plane may run cooler than an isolated external trace with no adjacent copper. IPC-2152 captures this with plane-proximity correction factors.

Routing high-current paths on external layers remains the default best practice because worst-case IPC-2221 result is half the trace width, thermal verification (IR imaging) is easier, and repair and rework are simpler.

Copper Weight and Trace Width

Copper weight, measured in ounces per square foot, sets the trace thickness:

  • 0.5 oz → 17.5 μm (0.689 mils)
  • 1 oz → 35 μm (1.378 mils) — standard
  • 2 oz → 70 μm (2.756 mils) — power electronics
  • 3 oz → 105 μm (4.134 mils) — high-current power
  • 4 oz → 140 μm (5.512 mils) — outside IPC-2221 range

Doubling copper weight roughly halves the required trace width for the same current, because cross-sectional area is the product of width and thickness. A 1 oz 28 mil trace carries the same current as a 2 oz 14 mil trace at the same temperature rise.

PCB Trace Width for USB-C Power Delivery

USB Power Delivery (USB-PD) introduces VBUS currents that push past the comfortable range of standard PCB design. Profile currents are:

  • USB-PD Standard: 3 A at 5/9/15/20 V
  • USB-PD Extended: 5 A at 9/15/20 V (requires e-marker cable)
  • USB-PD EPR: up to 5 A at higher voltages (Extended Power Range)

At 5 A on 1 oz external copper with 10 °C rise, the IPC-2221 minimum trace width is about 100 mils (2.5 mm). For production designs, plan 120–150 mils (3–4 mm) with 20–50% manufacturing margin, or move to 2 oz copper which roughly halves the required width to 50–60 mils (1.3–1.5 mm).

The connector escape region is the hardest part. USB-C receptacle pin pitch forces neck-down between the connector and the bulk VBUS trace. Make this neck-down as short as possible, use the full available pad area, and consider stitching with multiple vias if changing layers.

Vias on the VBUS path are often the bottleneck. A standard 0.3 mm drill via with 1 oz plating carries roughly 0.5–1 A continuously as a rough screening estimate. For 5 A through a via stack, use 4–8 parallel vias with adequate plating thickness, or specify larger drill diameter (0.4–0.5 mm).

What is PCB Trace Width

A printed circuit board (PCB) consists of copper conductors bonded to an insulating substrate (typically FR-4 fiberglass epoxy). The conductors carry current between components. A trace is one of those conductors — a strip of copper of specified width and thickness routed across the board.

Trace width matters because current flowing through any resistance generates heat (P = I²R). Copper has finite resistivity, so every trace heats up under current. A narrow trace concentrates heat in a small volume and rises in temperature; a wide trace spreads heat across a larger volume and stays cooler.

The IPC-2221 thermal model relates current, cross-sectional area, and temperature rise empirically. The formula I = k · ΔT^0.44 · A^0.725 is a curve fit to experimental data from MIL-STD-275 (1950s), not a derived physics equation. The 0.44 exponent on temperature rise reflects radiative and convective heat transfer; the 0.725 exponent on area reflects two-dimensional heat spreading at the copper-substrate interface.

Key Facts

  • PCB trace width follows from IPC-2221 thermal model: I = k · ΔT^0.44 · A^0.725, where k = 0.048 (external) or 0.024 (internal), ΔT in °C, A in mils².
  • At 1 A on 1 oz external copper with 10 °C rise, minimum trace width is approximately 12 mils (0.30 mm). At 3 A this rises to about 49 mils (1.24 mm). At 5 A, 100 mils (2.54 mm).
  • Doubling copper weight roughly halves required trace width for the same current, because cross-sectional area is the product of width and thickness.
  • Internal layer traces require approximately 2× the cross-section of external traces for the same current, per IPC-2221. Modern boards with adjacent planes often perform better than this estimate.
  • IPC-2221 is conservative for modern multilayer boards. IPC-2152 (2009) provides empirically-tested data with plane-proximity corrections and typically permits narrower traces.
  • Practical fab minimums are 4–6 mils (0.10–0.15 mm) for standard processes. Even if the calculator returns a narrower trace, the board cannot be manufactured below this limit.
  • Vias are often the bottleneck in high-current paths. A standard 0.3 mm drill via with 1 oz copper carries roughly 0.5–1 A continuously as a rough screening estimate.
  • Temperature rise (ΔT) and absolute temperature (T_ambient) follow different unit conversions. ΔT in °F converts as × 5/9 (no offset); T_ambient in °F converts as (T − 32) · 5/9 (offset).
  • Final trace temperature = T_ambient + ΔT. For automotive under-hood applications with 125 °C ambient and 10 °C rise, final trace temperature is 135 °C — close to the lower end of FR-4 glass transition (Tg 130–180 °C).
  • Apply 20–50% manufacturing margin on top of the IPC-2221 minimum. Critical applications and harsh environments warrant the higher end of this range.

Applications

  • Power Supply Design. Linear regulators, switching converters, and battery management circuits route currents from sub-amp to tens of amps. Use 2 oz copper for currents above 3 A and plan trace widths with 20–50% margin. Switching node traces should be short and wide to minimize loop area; output filter traces should be wider than calculated minimum for low ESR.
  • USB-C and USB-PD Designs. USB-C VBUS at 3 A or 5 A pushes single-trace widths to 50–100 mils (1.3–2.5 mm) on 1 oz external copper. Plan 2 oz copper if board area is constrained. The connector escape region forces neck-down; verify the narrowest segment carries the full VBUS current. Stitch via arrays for any layer transitions.
  • Motor Driver Layout. H-bridge MOSFET outputs see fast switching transients on top of steady-state current. Size traces for RMS or continuous heating current; verify peak fault current separately for fusing and protection. Thermal pad copper area below the H-bridge IC often dominates the overall thermal design more than the trace itself.
  • Automotive Electronics. Ambient temperatures from −40 °C (interior cold) to +125 °C (under-hood) compress the available ΔT budget. Conservative ΔT of 5–10 °C is common for reliability-sensitive designs. Use high-Tg laminate (170 °C+) for under-hood applications. AEC-Q qualified components are typically required.
  • Industrial Controllers. PLC outputs, motor controls, and power conversion circuits in industrial enclosures often operate at 40–60 °C ambient with vibration and humidity exposure. Apply 50% manufacturing margin and use 2 oz copper for power paths.
  • Battery Management. Cell-level current sensing, balancing, and pack protection traces span sub-amp through tens of amps. The pack-level current path may exceed IPC-2221 validity range (35 A); use IPC-2152 or empirical testing for this segment.
  • LED Drivers. Constant-current LED supplies typically run sub-amp to a few amps. Trace width is rarely the bottleneck; heat from the LEDs themselves dominates thermal design. Size the supply traces conservatively; focus thermal analysis on the LED footprint and heatsink.
  • Signal and Logic Traces. Digital and analog signal currents are typically far below IPC-2221 limits — even 6 mil traces carry milliamps with no temperature rise. Signal trace width is governed by controlled impedance, crosstalk, and routing density, not IPC-2221 current capacity.

Example Calculation

Example 1 — Power Supply Output (2 A, External 1 oz)

Inputs: Current = 2 A, ΔT = 10 °C, Copper weight = 1 oz (default), Layer type = external (default), Trace length = 50 mm, Design margin = 20%

Step 1: k = 0.048 (external layer)

Step 2: A = (2 / (0.048 · 10^0.44))^(1/0.725) = (2 / 0.1322)^1.379 ≈ 39.3 mils² (0.025 mm²)

Step 3: Copper thickness: 1 oz → 1.378 mils (35 μm)

Step 4: W = 39.3 / 1.378 ≈ 28.5 mils (0.72 mm)

Step 5: Recommended with 20% margin: 28.5 × 1.20 ≈ 34.2 mils (0.87 mm)

Step 6: Resistance (T_mean = 25 + 5 = 30°C): R ≈ 35.3 mΩ; V_drop = 71 mV; P_diss = 141 mW

Result: PCB Status: NORMAL / MODERATE-CURRENT. Minimum trace width: 28.5 mils (0.72 mm). Recommended: 34.2 mils (0.87 mm).

Example 2 — Current-from-Width (Internal 20 mil, 2 oz)

Inputs: Trace width = 20 mil, ΔT = 20 °C, Copper weight = 2 oz, Layer = internal, Current = blank

Step 1: k = 0.024 (internal), t = 2.756 mils (2 oz)

Step 2: A_actual = 20 × 2.756 = 55.12 mils²

Step 3: I_max = 0.024 · 20^0.44 · 55.12^0.725 ≈ 1.61 A

Result: PCB Status: NORMAL / MODERATE-CURRENT. Maximum current: 1.61 A. The same trace on an external layer (k=0.048) would carry about 2.3 A.

Example 3 — Verify Existing Severely Undersized (10 mil for 3 A)

Inputs: Current = 3 A, Trace width = 10 mil, ΔT = 10 °C, Copper = 1 oz, Layer = external

Step 1: W_required = (3/0.1322)^1.379 / 1.378 ≈ 49.1 mils

Step 2: Δ_min = (10 − 49.1) / 49.1 × 100% ≈ −79.6%. Use |Δ| = 79.6% (absolute value) to avoid double-negative wording: "designed trace width 10 mil is 79.6% below the IPC-2221 minimum."

Step 3: |Δ_min| > 10% → SEVERELY-UNDERSIZED

Result: PCB Status: SEVERELY-UNDERSIZED. Designed trace width 10 mil is 79.6% below the IPC-2221 minimum 49.1 mils. Increase to at least 49.1 mils (58.9 mils with 20% margin).

Standards & References

Units

Length (trace width, length): 1 mil = 0.0254 mm = 25.4 μm; 1 mm = 39.37 mils; 1 inch = 1000 mils = 25.4 mm.

Copper weight to thickness: 0.5 oz → 17.5 μm (0.689 mils); 1 oz → 35 μm (1.378 mils); 2 oz → 70 μm (2.756 mils); 3 oz → 105 μm (4.134 mils); 4 oz → 140 μm (5.512 mils).

Cross-sectional area: 1 mil² = 6.4516×10⁻⁴ mm².

Temperature difference (ΔT): °F to °C is × 5/9 (no offset). ΔT = 18 °F equals ΔT = 10 °C. Common implementation bug: applying offset conversion to ΔT gives meaningless results.

Absolute temperature (T_ambient): °F to °C is (T − 32) · 5/9. T = 86 °F equals T = 30 °C.

Resistance, voltage, power outputs: Trace resistance in mΩ for typical lengths; voltage drop in mV; power dissipation in mW.

Limitations

  • Plane and copper-pour effects. IPC-2221 was derived from single traces with no adjacent copper. Modern multilayer boards with ground planes, power planes, and copper pours adjacent to traces typically carry more current than IPC-2221 predicts. IPC-2152 quantifies these corrections; this calculator does not.
  • Transient and fault currents. The thermal sizing assumes continuous or RMS current. Short-duration current pulses (milliseconds and below) heat the trace differently and may permit much higher peak current. Fault currents require separate fusing analysis.
  • Characteristic impedance for RF and high-speed signals. Microstrip and stripline geometries are sized by impedance, not thermal capacity. Use a dedicated impedance calculator for controlled-impedance traces.
  • Skin effect at RF frequencies. Above approximately 100 MHz, current concentrates near the trace surface and edges, reducing effective conductor area. The IPC-2221 DC formula does not capture this.
  • Via thermal modeling. Vias have very different current-carrying characteristics from traces. A standard via with 1 oz plating carries far less current than a wide trace. Use a dedicated via-current calculator for designs where vias are on the current path.
  • Trace-to-trace coupling. Closely-spaced parallel traces heat each other; the calculator assumes isolated trace behavior.
  • Electromigration at very high current density. Current density above approximately 10⁵ A/cm² causes long-term material migration in copper. This is rarely a concern at PCB trace dimensions but matters for integrated circuit interconnect.
  • Mechanical reliability under thermal cycling. Temperature swings cause expansion-contraction stress on traces, vias, and solder joints. IPC-2221 sizes traces thermally but does not address fatigue lifetime.
  • Warnings and primary status are deduplicated: when a parameter exceeds the IPC-2221 validity range, the primary PCB Status displays OUT-OF-IPC-RANGE and the calculator suppresses the duplicate informational warning to keep the output clean.

Common Mistakes to Avoid

  • Treating temperature rise (ΔT) as an absolute temperature. ΔT is the rise above ambient. When entered in Fahrenheit, it must convert as × 5/9 (no offset), not (ΔT − 32) · 5/9. Treating 18 °F as if it were 18 °F absolute would substantially under-size the trace.
  • Using IPC-2221 result as final without manufacturing margin. The formula returns the theoretical minimum. Production designs need 20–50% margin for etching tolerances, ambient variations, and modeling uncertainty.
  • Ignoring fab process minimums. Standard PCB processes have minimum trace width of 4–6 mils (0.10–0.15 mm). Even if the calculator returns a 3 mil trace, the board cannot be manufactured below the fab's minimum.
  • Treating peak current as continuous. Short startup pulses, inrush currents, and transient peaks do not heat the trace the same way continuous current does. Use RMS or continuous current for thermal sizing; verify peak current separately for copper fusing.
  • Forgetting vias in the current path. A trace sized for 5 A carries 5 A. A via on that path may be the bottleneck if it is too small. A standard 0.3 mm via with 1 oz plating carries roughly 0.5–1 A continuously.
  • Confusing nominal copper weight with finished copper thickness. Nominal 1 oz base copper on outer layers may finish at 1.3–1.8 oz after plating. The calculator uses nominal thickness; finished outer copper may be slightly thicker.
  • Applying the 2× internal-layer penalty literally to all multilayer boards. The IPC-2221 internal/external 2× ratio assumes isolated traces in FR-4. Real multilayer boards with adjacent planes often perform much better. IPC-2152 quantifies plane-proximity correction.
  • Sizing only the bulk trace and ignoring neck-downs. The narrowest continuous segment controls local heating. Connector escape regions, IC pad neck-downs, fuse mounts, and via escapes often have much narrower geometry than the bulk trace and may overheat first.
  • Using IPC-2221 for RF or high-speed signal traces. RF trace width is governed by characteristic impedance, not current capacity. A 50 Ω microstrip on 1 oz copper at typical substrate thickness is roughly 14–20 mils wide regardless of current.
  • Ignoring final trace temperature in hot environments. A trace sized for 10 °C rise at 25 °C ambient operates at 35 °C. The same trace in a 100 °C automotive under-hood environment operates at 110 °C — beyond many component limits.

Frequently Asked Questions

How do I calculate PCB trace width?
Use the IPC-2221 formula: W = A / t, where A is required cross-section computed from (I / (k · ΔT^0.44))^(1/0.725) and t is copper thickness for the chosen weight. For external 1 oz copper at 10 °C rise, this gives approximately 12 mils per amp up to 1 A, with the relationship slightly compressing at higher currents. The calculator on this page does the math and applies manufacturing margin automatically.
What is the IPC-2221 standard for PCB trace width?
IPC-2221 (current edition IPC-2221C, 2023; previous editions IPC-2221B and earlier) is the IPC generic standard for printed board design. Its current-capacity formula I = k · ΔT^0.44 · A^0.725 with k = 0.048 (external) or 0.024 (internal) traces back to MIL-STD-275 test data from the 1950s. The formula is empirically curve-fit, not derived from physics, and is generally conservative for modern multilayer boards.
What is the difference between IPC-2221 and IPC-2152?
IPC-2221 derives from 1950s single-trace tests with no adjacent copper. IPC-2152 (2009) replaced the underlying data with new empirical tests on hundreds of board configurations, adding correction factors for plane proximity, board thickness, and laminate material. IPC-2152 typically permits narrower traces than IPC-2221 for the same current, especially on multilayer boards with planes adjacent to the trace.
How wide should a 1 amp PCB trace be?
At 1 A on 1 oz external copper with 10 °C temperature rise, the IPC-2221 minimum is approximately 12 mils (0.30 mm). Add 20–50% manufacturing margin to get 14–18 mils (0.36–0.45 mm). Internal traces at the same current need roughly double the width. At higher temperature rise budget (20 °C, 40 °C) the width drops correspondingly.
How wide should a 5 amp PCB trace be?
At 5 A on 1 oz external copper with 10 °C rise, the IPC-2221 minimum is approximately 100 mils (2.54 mm). Moving to 2 oz copper roughly halves this to 50 mils (1.27 mm). Add 20–50% margin for production. 5 A is common in USB-C VBUS extended profile and most motor driver outputs.
What is copper weight in PCB design?
Copper weight is the mass of copper per unit area of the PCB, given in ounces per square foot (oz/ft²). 1 oz/ft² corresponds to a nominal copper thickness of 1.378 mils (35 μm). Common weights are 0.5 oz (low-cost prototyping), 1 oz (standard), 2 oz (power electronics), and 3 oz (high-current). 4 oz and heavier fall outside the IPC-2221 validity range.
Why are internal traces wider than external traces in IPC-2221?
IPC-2221 uses k = 0.048 for external layers and k = 0.024 for internal layers. The 2× difference reflects the assumption that internal traces dissipate heat only through FR-4 substrate, while external traces also cool through air convection. In practice, internal traces adjacent to copper planes often run cooler than IPC-2221 predicts; IPC-2152 captures this with plane-proximity correction factors.
What temperature rise should I use for PCB trace sizing?
10 °C is a common conservative design rise suitable for most applications. 20 °C is often used for power circuits where some thermal compromise is acceptable. 40 °C is the upper end for harsh environments. Higher temperature rise permits narrower traces but compromises long-term reliability. For automotive and high-temperature applications, use 5–10 °C rise on top of the elevated ambient temperature.
How does the calculator handle Fahrenheit input?
Temperature rise (ΔT) and absolute temperature (T_ambient) use different conversion formulas. ΔT in °F converts as × 5/9 with no offset, because it is a temperature interval. T_ambient in °F converts as (T − 32) · 5/9 because it is an absolute temperature. The calculator handles this automatically based on which unit dropdown the user selects.
Does trace length affect maximum current capacity?
According to IPC-2221, trace length does not affect thermal current capacity. Current capacity depends on cross-section and heat dissipation. Length affects only resistance, voltage drop, and power dissipation. A 1 mm trace and a 100 mm trace of the same width carry the same maximum current; the longer trace just has more total voltage drop and total power dissipation.
How much manufacturing margin should I add to IPC-2221 results?
20% margin is typical for production designs and accounts for etching tolerances (±0.5–1 mil), modeling uncertainty, and ambient temperature variation. 50% margin is appropriate for harsh environments, critical reliability applications, and high-temperature designs. The calculator's default is 20%; the design margin dropdown selects 20%, 50%, or a custom percentage.
What is a safe via current for PCB design?
A standard 0.3 mm drill via with 1 oz copper plating carries approximately 0.5–1 A continuously as a rough screening estimate. Actual capacity depends on plating thickness, via length (board thickness), annular ring size, adjacent copper, and temperature rise budget. For high-current paths, use multiple parallel vias, larger drill diameters, or filled vias.

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